The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor.
Device structures for a field-effect transistor include a source, a drain, a body situated between the source and drain, and a gate structure including a gate electrode and a gate dielectric separating the gate electrode from the body. A gate voltage applied to the gate electrode is used to provide switching that selectively connects the source and drain to each other through a channel formed in the body. The channel of a planar field-effect transistor is located beneath the top surface of the substrate on which the gate structure is supported. In contrast, the channel of a fin-type field-effect transistor is located in a semiconductor fin about which the gate electrode is wrapped.
Bi-layer spacers may be formed adjacent to the sidewalls of the gate electrode and, in many instances, may be characterized by material and/or physical properties intended to boost device performance. A bi-layer spacer typically includes an inner spacer of single thickness proximate to the sidewall of the gate electrode and an outer spacer of single thickness separated from the sidewall by the inner spacer. The inner spacer may be selected to have a lower dielectric constant than the outer spacer, which tends to boost device performance. The outer spacer may be selected to resist processes that cause material erosion and to thereby improve the robustness of the bi-layer spacer. For example, the etch rate of the outer spacer may be several times less than the etch rate of the inner spacer when exposed to the same etching, cleaning, or ashing processes. If the protection afforded by the outer spacer fails, the inner spacer can rapidly erode due to its higher etch rate. This erosion can lead to the formation of a void that links the gate electrode and an adjacent source/drain region, which is normally separated from the gate electrode by the bi-layer spacer.
Improved structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor are needed.